DeSyRe is an FP7 STREP project.
The DeSyRe project performed research on the design of future reliable Systems-on-Chip (SoCs). These are systems that guarantee continuous and correct operation in the existence of different types of faults. It is a well-known fact that various systems are extremely sensitive to faults; typical examples are medical-embedded systems, in which a single malfunction will put the life of a patient in danger.
However, as semiconductor technology scales, chips are becoming ever less reliable; prominent reasons for this phenomenon are the sheer number of transistors on a given silicon area and their shrinking device features. As a consequence, fault tolerance, provided through various redundancy schemes, comes at an enormous increase in power cost and performance overheads. To make matters worse, power density is becoming a significant limiting factor for performance and SoC design in general. In the face of such changes in the technological landscape, current solutions for fault tolerance are expected to introduce an excessive overhead in future SoCs.
At the increasing fault rates, expected in the upcoming technology generations, DeSyRe developed new design techniques for future SoCs, improving their reliability and reducing their power and performance overheads for fault tolerance.
Neurasmus B.V. joined the consortium as an application provider. During the duration of DeSyRe the Inferior Olive application was developed and accelerated on FPGAs. This was the basis and the first attempt to use High-Performance accelerators for neuroscientific experiments within Neurasmus and the forerunner of the later BrainFrame Project. Additionally, it provided SINS-related applications. As implantable technology requires high reliability the insights the project would offer would be invaluable for the project.