EU Projects
DeSyRe: on-Demand System Reliability
DeSyRe is an FP7 STREP project. The DeSyRe project performed research on the design of future reliable Systems-on-Chip (SoCs). These are systems that guarantee continuous and correct operation in the existence of different types of faults. It is a well-known fact that various systems are extremely sensitive to faults; typical examples are medical embedded systems, in which a single malfunction will put the life of a patient in danger. However, as semiconductor technology scales, chips are becoming ever less reliable; prominent reasons for this phenomenon are the sheer number of transistors on a given silicon area and their shrinking…Read more
EuroEXA targets to provide the template for an upcoming exascale system by co-designing and implementing a petascale-level prototype with ground-breaking characteristics. To accomplish this, the project takes a holistic approach to innovating both across the technology and the application/system software pillars. EuroEXA proposes a balanced architecture for compute and data-intensive applications, that builds on top of cost-efficient, modular integration enabled by novel inter-die links, utilises a novel processing unit and embraces FPGA acceleration for computational, networking and storage operations. EuroEXA hardware designers work together with system software experts optimising the entire stack from language runtimes to low-level kernel drivers, and application developers…Read more
SDK4ED: Software Development ToolKit for Energy Optimization and Technical Debt Elimination
The vision of SDK4ED is to minimize the cost, the development time and the complexity of low-energy software development processes, by providing tools for automatic optimization of multiple quality requirements, such as technical debt, energy efficiency, dependability and performance. SDK4ED will develop methods and accompanying software tools capable of parsing software artifacts, (source code, design models, test cases, etc.) and analyzing these items from the perspective of technical debt liability, considering the targeted hardware platform and the provided quality requirements. The corresponding tools will provide reports with deficiencies, ranked by importance and urgency to be resolved, considering the past history…Read more
Security-by-design for end-to-end security (SHARCS)
SHARCS aims at designing, building and demonstrating secure-by-design system architectures that achieve end-to-end security for their users. SHARCS will achieve this by systematically analyzing and extending, as necessary, every hardware and software layer in a computing system. The new technologies developed will be directly utilizable by applications and services that require end-to-end security. Developing new security paradigms, architectures, and software, for more secure and trustworthy ICT systems and services has clear social, scientific, and market motivation. This motivation is becoming stronger due to the changing threat landscape; over the past decade, we are witnessing an ever-increasing amount of cyberattacks on…Read more
The VINEYARD project develops novel servers based on programmable dataflow accelerators that can be customized based on the data centre’s application requirements. These programmable dataflow accelerators will be used not only to increase the performance of servers but also to reduce energy consumption in data centres. Furthermore, VINEYARD develops a programming framework that will hide the complexity of programming heterogeneous systems while at the same time providing the optimized performance of customized and heterogeneous architectures. VINEYARD also develops a new programming framework that seamlessly leverages workload-specific accelerators based on the application requirements. In this suite, the user works with familiar…Read more